Freescale Semiconductor /MK60DZ10 /PORTE /PCR19

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Interpret as PCR19

LK=0, MUX=000, IRQC=0000, PS=0, PE=0, DSE=0, ODE=0, PFE=0, SRE=0, ISF=0

Description

Pin Control Register n

Fields

PS	Pull Select 0 (0): Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. 1 (1): Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
PE	Pull Enable 0 (0): Internal pull-up or pull-down resistor is not enabled on the corresponding pin. 1 (1): Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
SRE	Slew Rate Enable 0 (0): Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. 1 (1): Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
PFE	Passive Filter Enable 0 (0): Passive Input Filter is disabled on the corresponding pin. 1 (1): Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
ODE	Open Drain Enable 0 (0): Open Drain output is disabled on the corresponding pin. 1 (1): Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
DSE	Drive Strength Enable 0 (0): Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. 1 (1): High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
MUX	Pin Mux Control 0 (000): Pin Disabled (Analog). 1 (001): Alternative 1 (GPIO). 2 (010): Alternative 2 (chip specific). 3 (011): Alternative 3 (chip specific). 4 (100): Alternative 4 (chip specific). 5 (101): Alternative 5 (chip specific). 6 (110): Alternative 6 (chip specific). 7 (111): Alternative 7 (chip specific / JTAG / NMI).
LK	Lock Register 0 (0): Pin Control Register bits [15:0] are not locked. 1 (1): Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
IRQC	Interrupt Configuration 0 (0000): Interrupt/DMA Request disabled. 1 (0001): DMA Request on rising edge. 2 (0010): DMA Request on falling edge. 3 (0011): DMA Request on either edge. 8 (1000): Interrupt when logic zero. 9 (1001): Interrupt on rising edge. 10 (1010): Interrupt on falling edge. 11 (1011): Interrupt on either edge. 12 (1100): Interrupt when logic one.
ISF	Interrupt Status Flag 0 (0): Configured interrupt has not been detected. 1 (1): Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.

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